Architectural, Numerical and Implementation Issues in the VLSI Design of an Integrated CORDIC-SVD Processor

The Singular Value Decomposition (SVD) is an important matrix factorization with applications in signal processing, image processing and robotics. This thesis presents some of the issues involved in the design of an array of special-purpose processors connected in a mesh, for fast real time computation of the SVD. The systolic array implements the Jacobi method for the SVD. This involves plane rotations and inverse tangent calculations and is implemented e ciently in hardware using the COordinate Rotation DIgital Computer (CORDIC) technique. A six chip custom VLSI chip set for the processor was initially developed and tested. This helped identify several bottlenecks and led to an improved design of the single chip version. The single chip implementation incorporates several enhancements that provide greater numerical accuracy. An enhanced architecture which reduces communication was developed within the constraints imposed by VLSI. The chips were fabricated in a 2:0 CMOS n-well process using a semicustom design style. The design cycle for future chips can be considerably reduced by adopting a symbolic layout style using high-level VLSI tools such as Octtools from the University of California, Berkeley.